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features ? programmable preheat time & frequency ? programmable ignition ramp ? protection from failure-to-strike ? lamp filament sensing & protection ? protection from operation below resonance - 0.2v cs threshold syncd to falling edge on lo ? protection from low-line condition ? automatic restart for lamp exchange fully integrated ballast control ic typical connection ? thermal overload protection ? programmable deadtime ? integrated 600v level-shifting gate driver ? internal 15.6v zener clamp diode on vcc ? micropower startup (150ua) ? latch immunity protection on all leads ? esd protection on all leads ? parts also available lead-free description the ir21571 is a fully integrated, fully protected 600v ballast control ic designed to drive virtually all types of rapid start fluorescent lamp ballasts. externally pro- grammable features such as preheat time & frequency, ignition ramp characteris- tics, and running mode operating frequency provide a high degree of flexibility for the ballast design engineer. comprehensive protection features such as protec- tion from failure of a lamp to strike, filament failures, low dc bus conditions, thermal overload, or lamp failure during normal operation, as well as an automatic restart function, have been included in the design. the heart of this control ic is a variable frequency oscillator with externally programmable deadtime. precise control of a 50% duty cycle is accomplished using a t-flip-flop. the ir21571 is available in both 16 pin dip and 16 pin narrow body soic packages. packages 16 lead soic (narrow body) 16 lead pdip + v bus + rectified ac line v bus return r ph r run c start r start r t c t c ramp c ph r dt c bs d boot r supply c vcc r cs l res c res r ghs r gls c block c snubber r1 r2 c1 r oc r4 r3 r5 c2 d1 d2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ir21571 vdc cph rph rt run ct dt oc lo com vcc vb vs ho sd cs www.irf.com 1 ir21571(s) & (pbf) not recommended for new design: please use irs21571d data sheet pd no. 60179 revm free datasheet http://
ir21571 (s) & (pbf) 2 www.irf.com note 1: this ic contains a zener clamp structure between the chip v cc and com which has a nominal breakdown voltage of 15.6v. please note that this supply pin should not be driven by a dc, low impedance power source greater than the v clamp specified in the electrical characteristics section. absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com, all currents are defined positive into any lead. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. symbol definition min. max. units v b high side floating supply voltage -0.3 625 v s high side floating supply offset voltage v b - 25 v b + 0.3 v ho high side floating output voltage v s - 0.3 v b + 0.3 v lo low side output voltage -0.3 v cc + 0.3 i omax maximum allowable output current (either output) due to external power transistor miller effect i rt r t pin current -5 5 v ct c t pin voltage -0.3 5.5 v dc v dc pin voltage -0.3 v cc + 0.3 i cph cph pin current -5 5 i rph rph pin current -5 5 i run run pin current -5 5 i dt deadtime pin current -5 5 v cs current sense pin voltage -0.3 5.5 v i cs current sense pin current -5 5 i oc over-current threshold pin current -5 5 i sd shutdown pin current -5 5 i cc supply current (note 1) -20 20 dv/dt allowable offset voltage slew rate -50 50 v/ns p d package power dissipation @ t a +25 c (16 lead pdip) ? 1.60 p d = (t jmax -t a )/rth ja (16 lead soic) ? 1.00 rth ja thermal resistance, junction to ambient (16 l ead pdip) ? 75 (16 lead soic) ? 115 t j junction temperature -55 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 v c/w ma -500 500 v ma ma w c free datasheet http://
ir21571 (s) & (pbf) www.irf.com 3 note 2: enough current should be supplied into the vcc lead to keep the internal 15.6v zener clamp diode on this lead regulating its voltage. note 3: due to the fact that the rt input is a voltage-controlled current source, the total rt lead current is the sum of all the parallel current sources connected to that lead. for optimum oscillator current mirror performance, this total current should be kept between 50 a and 500 a. during the preheat mode, the total current flowing out of the rt lead consists of the rph lead current plus the current due to the rt resistor. during the run mode, the total rt lead current consists of the run lead current plus the current due to the rt resistor. electrical characteristics v cc = v bs = v bias = 14v +/- 0.25v, r t = 40.0k , c t = 470 pf, rph and run leads no connection, v cph = 0.0v, r dt = 6.1k , r oc = 20.0k , v cs = 0.5v, v sd = 0.0v, c l = 1000pf, t a = 25 o c unless otherwise specified. symbol definition min. typ. max. units test conditions v ccuv+ v cc supply undervoltage positive going 10.5 11.4 12.4 v cc rising from 0v threshold v uvhys v cc supply undervoltage lockout hysteresis 1.5 1.8 2.2 i qccuv uvlo mode quiescent current 50 150 300 v cc < v ccuv- i qccflt fault-mode quiescent current 75 200 300 sd=5v, cs = 2v or tj > t sd i qcc quiescent v cc supply current 2.9 3.8 4.3 r t no connection, c t connected to com i cc50k v cc supply current, f= 50khz 4.0 5.5 7.0 r t =36k , r dt = 5.6k , c t =220pf supply characteristics a ma v clamp v cc zener clamp voltage 14.5 15.6 16.5 v i cc = 10ma v recommended operating conditions for proper operation the device should be used within the recommended conditions. symbol definition min. max. units v bs high side floating supply voltage v cc - 0.7 v clamp v s steady state high side floating supply offset voltage -3.0 600 v cc supply voltage v ccuv+ v clamp i cc supply current note 2 10 ma v dc v dc lead voltage 0 vcc v c t c t lead capacitance 220 ? pf r dt deadtime resistance 1.0 ? r oc over-current (cs+) threshold programming resistance ? 50 i rt r t lead current (note 3) -500 -50 i rph rph lead current (note 3) 0 450 i run run lead current (note 3) 0 450 i sd shutdown lead current -1 1 i cs current sense lead current -1 1 t j junction temperature -40 125 o c vbsmin minimum required vbs voltage for proper ho functionality ? 5 v v k ua ma free datasheet http://
ir21571 (s) & (pbf) 4 www.irf.com floating supply characteristics symbol definition min. typ. max. units test conditions i qbs0 quiescent v bs supply current 0 0 15 v ho = v s i qbs1 quiescent v bs supply current 5 35 65 v ho = v b i lk offset supply leakage current ? ? 50 a v b = v s = 600v a electrical characteristics (cont.) v cc = v bs = v bias = 14v +/- 0.25v, r t = 40.0k , c t = 470 pf, rph and run leads no connection, v cph = 0.0v, r dt = 6.1k , r oc = 20.0k , v cs = 0.5v, v sd = 0.0v, c l = 1000pf, t a = 25 o c unless otherwise specified. rph characteristics symbol definition min. typ. max. units test conditions i rphlk open circuit rph lead leakage current ? 0.01 0.1 a v rph = 5v,v rph = 6v v rphflt fault-mode rph lead voltage ? 0 50 mv sd = 5v, cs = 2v, or tj > tsd oscillator i/o characteristics symbol definition min. typ. max. units test conditions fosc oscillator frequency 45.5 48 50.5 r t = 16.9k , r dt = 6.1k , c t =470pf d oscillator duty cycle 49.5 50 50.5 % v ct+ upper c t ramp voltage threshold 3.7 4.0 4.3 v ct- lower c t ramp voltage threshold 1.85 2.0 2.15 v ctflt fault-mode c t lead voltage ? 0 50 mv sd = 5v, cs = 2v, or tj > tsd v rt r t lead voltage 1.85 2.0 2.15 v v rtflt fault-mode r t lead voltage ? 0 50 sd = 5v, cs = 2v, or tj > tsd tdlo lo output deadtime 2 2.3 2.5 tdho ho output deadtime 2 2.3 2.5 mv khz sec v symbol definition min. typ. max. units test conditions i cph cph lead charging current 0.72 0.85 0.98 av cph = 5.3v v cphign cph lead lgnition mode threshold voltage 3.7 4.0 4.3 v cphrun cph lead run mode threshold voltage 4.7 5.15 5.45 v cphclmp cph lead clamp voltage 9.0 9.5 10.5 i cph = 1ma v cphflt fault-mode cph lead voltage ? 0 300 mv sd = 5v, cs = 2v, or tj > tsd preheat characteristics v free datasheet http://
ir21571 (s) & (pbf) www.irf.com 5 electrical characteristics (cont.) v cc = v bs = v bias = 14v +/- 0.25v, r t = 40.0k , c t = 470 pf, rph and run leads no connection, v cph = 0.0v, r dt = 6.1k , r oc = 20.0k , v cs = 0.5v, v sd = 0.0v, c l = 1000pf, t a = 25 o c unless otherwise specified. run characteristics symbol definition min. typ. max. units test conditions i runlk open circuit run lead leakage current ? 0.01 0.1 av run = 5v v runflt fault-mode run lead voltage ? 0 50 mv sd = 5v, cs = 2v, or tj > tsd symbol definition min. typ. max. units test conditions vol low-level output voltage ? 0 100 i o = 0 v oh high level output voltage ? 0 100 v bias - v o, i o = 0 t r turn-on rise time 55 85 150 t f turn-off fall time 35 45 100 gate driver output characteristics mv nsec note 4: when the ic senses an overtemperature condition (tj > 160oc), the ic is latched off. in order to reset this fault latch, the sd lead must be cycled high and then low, or the v cc supply to the ic must be cycled below the falling undervoltage lockout threshold (v ccuv- ). protection circuitry characteristics symbol definition min. typ. max. units test conditions v sd+ rising shutdown lead threshold voltage 1.9 2.1 2.3 v v sdhys shutdown pin threshold hysteresis 100 150 200 mv v cs+ over-current sense threshold voltage 0.99 1.10 1.21 v cs- under-current sense threshold voltage 0.15 0.2 0.26 t cs over-current sense propogation delay 100 250 400 nsec delay from cs to lo v dc+ low v bus /rectified line input upper threshold 5.0 5.20 5.6 v dc- low v bus /rectified line input lower threshold 2.85 3.3 3.3 t sd thermal shutdown junction temperature 150 160 170 o c note 4 v v free datasheet http://
ir21571 (s) & (pbf) 6 www.irf.com functional block diagram pin # symbol description 1 11 10 9 3 8 7 6 5 4 2 16 15 14 13 12 vdc ho vb vs vcc com lo cs sd dt ct run rt rph cph dc bus sensing input preheat timing capacitor preheat frequency resistor & ignition capacitor oscillator timing resistor run frequency resistor oscillator timing capacitor deadtime programming shutdown input current sensing input low-side gate driver output ic power & signal ground logic & low-side gate driver supply high-side gate driver floating supply high voltage floating return high-side gate driver output 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ir21571 vdc cph rph rt run ct dt oc lo com vcc vb vs ho sd cs oc over-current (cs+) threshold programming lead assignments & definitions over- temp detect level shift pulse filter & latch 2 4.0v 5.1v 3 5 10v 3.0v 5.1v 1 1.0ua 4 2.0v i r t 6 i c t = i r t 7 4.0v 2.0v cph rph rt run ct dt vdc q s r2 q r1 q t rq 16 14 15 vs ho vb 13 11 12 com lo vcc 15.6v 9 sd 10 0.2v cs q s rq qd r q clk q s r q under- voltage detect 2.0v 8 oc 50ua 7.6v 7.6v 7.6v free datasheet http://
ir21571 (s) & (pbf) www.irf.com 7 uvlo mode 1 / 2 -bridge off i qcc 150 a cph = 0v oscillator off preheat mode 1 / 2 -bridge @ f ph cph charging @ i ph = 1 a rph = 0v run = open circuit cs disabled ignition ramp mode f ph ramps to f min cph charging @ i ph = 1 a rph = open circuit run = open circuit cs+ threshold enabled run mode f min ramps to f run cph charges to 7.6v clamp rph = open circuit run = 0v cs- threshold enabled vcc > 11.4v (uv+) and vdc > 5.1v (bus ok) and sd < 1.7v (lamp ok) and t j < 160c (t jmax ) cph > 4.0v (end of preheat mode) cph > 5.1v (end of ignition ramp) vcc < 9.5v (vcc fault or power down) or vdc < 3.0v (dc bus/ac line fault or power down ) or sd > 2.0v (lamp fault or lamp removal) power turned on fault mode fault latch set 1 / 2 -bridge off i qcc 150 a cph = 0v vcc = 15.6v oscillator off t j > 160c (over-temperature) cs > cs+ threshold (failure to strike lamp or hard switching) or t j > 160c (over-temperature) cs > cs+ threshold (over-current or hard switching) or cs < 0.2v (no-load or below resonance) or t j > 160c (over-temperature) sd > 2.0v (lamp removal) or vcc < 9.5v (power turned off) ir21571 state diagram free datasheet http://
ir21571 (s) & (pbf) 8 www.irf.com supply bypassing and pc board layout rules component selection and placement on the pc board is extremely important when using power control ics. v cc should be bypassed to com as close to the ic terminals as possible with a low esr/esl capacitor, as shown in figure 1 below. a rule of thumb for the value of this bypass capacitor is to keep its minimum value at least 2500 times the value of the total input capacitance (ciss) of the power transistors being driven. this decoupling capacitor can be split between a higher valued electrolytic type and a lower valued ceramic type connected in parallel, although a good quality electrolytic (e.g., 10 f) placed immediately adjacent to the v cc and com terminals will work well. in a typical application circuit, the supply voltage to the ic is normally derived by means of a high value startup resistor (1/4w) from the rectified line voltage, in combination with a charge pump from the output of the half-bridge. with this type of supply arrangement, the internal 15.6v zener clamp diode from v cc to com will determine the steady state ic supply voltage. connecting the ic ground (com) to the power ground both the low power control circuitry and low side gate driver output stage grounds return to this lead within the ic. the com lead should be connected to the bottom terminal of the current sense resistor in the source of the low side power mosfet using an individual pc board trace, as shown in figure 2. in addition, the ground return path of the timing components and v cc decoupling capacitor should be connected directly to the ic com lead, and not via separate traces or jumpers to other ground traces on the board. this connection technique prevents high current ground loops from interfering with the sensitive timing component operation, and allows the entire control circuit to reject common-mode noise due to output switching. description of operation & component selection tips figure 1: supply bypassing pcb layout example figure 2: com lead connection pcb layout example c vcc (surface mount) d boot (surface mount) c boot (surface mount) c vcc (through hole) pin 1 ir21571 c vcc (surface mount) c vcc (through hole) ir21571 pin 1 timing components v bus return r cs (through hole) free datasheet http://
ir21571 (s) & (pbf) www.irf.com 9 the control sequence & timing component selection the ir21571 uses the following control sequence (figure 3) to drive rapid start fluorescent lamps. the control sequence used in the ir21571 allows the run mode operating frequency of the ballast to be higher than the ignition frequency (i.e., fstart > fph > frun > fign). this control sequence is recommended for lamp types where the ignition frequency is too close to the run frequency to ensure proper lamp striking for all production resonant lc component tolerances (please note that it is possible to use the ir21571 in systems where fstart > fph > fign > frun, simply by leaving the run lead open). six leads in the ic are used to control the startup, preheat, ignition ramp, and run modes of operation, and to allow ballast and lamp engineers the flexibility to optimize their designs for virtually any lamp type. the heart of this controller is an oscillator which resembles those found in many popular pwm voltage regulator ics. in its simplest form, this oscillator consists of a timing resistor and capacitor connected to ground. the voltage across the timing capacitor ct is a sawtooth, where the rising portion of the ramp is determined by the current in the r t lead, and the falling portion of the ramp is determined by an external deadtime resistor r dt . the oscillograph in figure 4 illustrates the relationship between the oscillator capacitor waveform and the gate driver outputs. the deadtime can be programmed by means of the external r dt resistor, given a certain range of ct capacitor values, using the graph shown in figure 5. the r t input is a voltage-controlled current source, where the voltage is regulated to be approximately 2.0v. in order to maintain proper linearity between the r t lead current and the c t capacitor charging current, the value of the r t lead current should be kept between 50a and 500a. the r t lead can also be used as a feedback point for closed loop control. figure 3: ir21571 control sequence figure 4 f ph f run f min frequency t f start v cph 5v v rph 2v v run 2v preheat mode ignition ramp mode run mode free datasheet http://
ir21571 (s) & (pbf) 10 www.irf.com figure 5: deadtime versus r dt during the startup mode , the operating frequency is determined by the parallel combination of r ph , r start , and r t , combined with the values of c start , c t and r dt , as shown in figure 6. this frequency is normally chosen to ensure that the instantaneous voltage across the lamp during the first few cycles of operation does not exceed the strike potential of the lamp. as the voltage across c start charges up to the r t lead voltage, the output frequency exponentially decays to the preheat frequency. during the preheat mode, the operating frequency is determined by the parallel combination of r ph and r t , combined with the value of c t and r dt . this frequency, along with the preheat time, is normally chosen to ensure that adequate heating of the lamp filaments occur. typically, a 4.5:1 ratio of the hot filament-to-cold filament resistance is desired for maximum lamp life, as shown in figure 7. figure 6: oscillator section block diagram with external component connection 0.1 1 10 1 10 100 rdt (kohms) tdead (usec) ct = 220 pf ct = 470 pf ct = 1 nf 2 4.0v 5.1v 3 5 7.6v 1.0ua 4 2.0v i rt 6 i ct = i rt 7 4.0v 2.0v cph rph rt run ct dt q s r2 q r1 under- voltage detect c ph c ign r t c start r start c t r dt r ph r run free datasheet http://
ir21571 (s) & (pbf) www.irf.com 11 the preheat time is programmed by means of the preheat capacitor, c ph , an internal 1 a current source, and an internal threshold on the c ph lead of 4.0v, according to the following formula: at the end of the preheat time, the internal, open- drain transistor holding the r ph lead to ground turns off, and the voltage on this lead charges exponentially up to the r t lead potential. during this ignition ramp mode, the output frequency exponentially decays to a minimum value. the rate of decay of this frequency is a function of the r ph * c ph time constant. because the ignition ramp mode ends when the voltage on the c ph lead reaches 5.15v, the ignition ramp mode is always 1/4th as long as the preheat time. when the c ph lead reaches 5.15v, an open-drain transistor on the run lead turns on, and the external r run resistor is then in parallel with the r t resistor. the run mode operating frequency is therefore a function of the parallel combination of r run and r t , and this means that the operating power of the lamp can be programmed by means of r run . figure 8: fosc versus effective r t (t dead = 2.0 usec) figure 9: fosc versus effective r t (t dead = 1.0 usec) the following graphs, figures 8 and 9, illustrate the relationship between the effective r t resistance (i.e., the parallel combination of resistors which programs the c t capacitor charging current) and the operating frequency. figure 7: lamp filament voltage during the preheat, ignition ramp and run modes. 0 50 100 150 0 5 10 15 20 25 30 35 40 rt (k ohms) freq (khz) ct=220pf,rdt=11k ct=470pf,rdt=6.2k ct=1nf,rdt=3k 0 50 100 150 200 250 0 5 10 15 20 25 30 35 40 rt (k ohms) freq (khz) ct=220pf, rdt=5.6k ct=470pf, rdt=2.7k ct=1nf, rdt=1.2k preheat run ignition ramp ph ph ph ph t 9 - 213e = c or , c 4.7e6 t = free datasheet http://
ir21571 (s) & (pbf) 12 www.irf.com lamp protection & automatic restart circuitry operation three leads on the ir21571 are used for protection, as shown in figure 10 below. these are v dc (dc bus monitor), s d (unlatched shutdown), c s (latched shutdown) and oc (cs+ threshold programming). figure 10: lamp protection & automatic restart circuitry block diagram with external component connection. sensing the dc bus voltage the first of these protection leads senses the voltage on the dc bus by means of an external resistor divider and an internal comparator with hysteresis. when power is first supplied to the ic at system startup, 3 conditions are required before oscillation is initiated: 1.) the voltage on the v cc lead must exceed the rising undervoltage lockout threshold (11.5v), 2.) the voltage at the v dc lead must exceed 5.1v, and 3.) the voltage on the sd lead must be below approximately 1.85v. if a low dc bus condition occurs during normal operation, or if power to the ballast is shut off, the dc bus will collapse prior to the v cc of the chip (assuming the v cc is derived from a charge pump off of the output of the half-bridge). in this case, the voltage on the v dc lead will shut the oscillator off, thereby protecting the power transistors from potentially hazardous hard switching. approximately 2v of hysteresis has been designed into the internal comparator sensing the v dc lead, in order to account for variations in the dc bus voltage under varying load conditions. when the dc bus recovers, the chip restarts from the beginning of the control sequence, as shown in timing diagram figure 11. over- temp detect 2 4.0v 5.1v 7.6v 3.0v 5.1v 1 1.0ua 7 cph dt vdc q t rq 8 oc 2.0v 10 0.2v cs q s rq qd r q clk q s r q under- voltage detect from oscillator section +v bus from lower lamp cathode r cs r3 r4 r5 r1 c1 r2 q2 9 sd 50ua 7.6v 7.6v 7.6v r oc c2 v cc free datasheet http://
ir21571 (s) & (pbf) www.irf.com 13 figure 11: vdc lead fault and auto restart lamp presence detection and automatic restart the second protection lead, sd, is used for both unlatched shutdown and automatic restart functions. the sd lead would normally be connected to an external circuit which senses the presence of the lamp (or lamps), as shown in figure 12. when the sd lead exceeds 2.0v (approximately 150mv of hysteresis is included to increase noise immunity), signaling either a lamp fault or lamp removal, the oscillator is disabled, both gate driver outputs are pulled low, and the chip is put into the micropower mode. since a lamp fault would normally lead to a lamp exchange, when a new lamp is inserted into the fixture, the sd lead would be pulled back to near the ground potential. under these figure 12: lamp presence detection circuit connection (shaded area) conditions a reset signal would restart the chip from the beginning of the control sequence, as shown in the timing diagram in figure 13. figure 13: sd lead fault and auto restart run mode low vdc ct 4 vdc 3 5 cph 8 lo 15 ho-vs 15 restart 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ir21571 vdc cph rph rt run ct dt oc lo com vcc vb vs ho sd cs + v bus + rectified ac line v bus return c bs d boot r supply c vcc r cs l res c res r ghs r gls c block c snubber r4 r3 r5 c2 d1 d2 run mode sd mode ct 4 cph 8 lo 15 ho-vs 15 restart sd 2 free datasheet http://
ir21571 (s) & (pbf) 14 www.irf.com thus, for a lamp removal and replacement, the ballast automatically restarts the lamp in the proper manner, maximizing lamp life and minimizing stress on the power mosfets or igbts. the sd lead contains an internal 7.5v zener diode clamp, thereby reducing the number of external components required. half-bridge current sensing and protection the third lead used for protection is the cs lead, which is normally connected to a resistor in the source of the lower power mosfet, as shown in figure 14. the cs lead is used to sense fault conditions such as failure of a lamp to strike, over-current during normal operation, hard switching, no load, and operation below resonance. if any one of these conditions is sensed, the fault latch is set, the oscillator is disabled, the gate driver outputs go low, and the chip is put into the micropower mode. the cs lead performs its sensing functions on a cycle-by-cycle basis in order to maximize ballast reliability. for the over-current, failure-to-strike, and hard switching fault conditions, an externally programmable, positive-going cs+ threshold is enabled at the end of the preheat time. the level of this positive-going threshold is determined by the value of the resistor roc. the value of the resistor roc is determined by the following formula: for the under-current and under-resonance conditions, there is a negative-going cs- threshold of 0.2v which is enabled at the onset of the run mode. the sensing of this cs- threshold is synchronized with the falling edge of the lo output. figures 15, 16 and 17 are oscillographs of fault conditions. figure 15 shows a failure of the lamp to strike, figure 16 shows a hard switching condition and figure 17 shows an under-current condition. figure 14: half-bridge current sensing circuit connection (shaded area) figure 15: lamp failure to strike rec tifi e d ac line 1 / 2 bridge output c vcc r supply d1 d2 q2 q1 c snubber v bus return +v bus d boot c boot r cs r3 r gls r ghs 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ir21571 vdc cph rph rt run ct dt oc lo com vcc vb vs ho sd cs r oc r oc = or v cs + 50e - 6 v cs + = 50e -6 - r oc free datasheet http://
ir21571 (s) & (pbf) www.irf.com 15 recovery from such a fault condition is accomplished by cycling either the sd lead or the v cc lead. when a lamp is removed, the sd lead goes high, the fault latch is reset, and the chip is held off in an unlatched state. lamp replacement causes the sd lead to go low again, reinitiating the startup sequence. the fault latch can also be reset by the undervoltage lockout signal, if v cc falls below the lower undervoltage threshold. bootstrap supply considerations power is normally supplied to the high-side circuitry by means of a simple charge pump from v cc , as shown in figure 19. figure 17: operation below resonance figure 18: auto restart for lamp replacement figure 16: hard switching condition free datasheet http://
ir21571 (s) & (pbf) 16 www.irf.com power supply to the upper gate driver cmos circuitry. since the quiescent current in this cmos circuitry is very low (typically 45 , , , , , , , , , , , free datasheet http://
ir21571 (s) & (pbf) www.irf.com 17 16-lead soic (narrow body) 01-6018 01-3064 00 (ms-012ac) 16-lead pdip 01-6015 01-3065 00 (ms-001a) case outlines free datasheet http://
ir21571 (s) & (pbf) 18 www.irf.com ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 data and specifications subject to change without notice. 6/10/2008 leadfree part marking information order information basic part (non-lead free) 16-lead pdip ir21571 order ir21571 16-lead soic ir21571s order ir21571s leadfree part 16-lead pdip ir21571 order IR21571PBF 16-lead soic ir21571s order ir21571spbf lead free released non-lead free released part number date code irxxxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code per scop 200-002 p ? marking code rev. date page # description of change m 6/10/80 1 ?not recommended for new design: please use irs21571d? free datasheet http://

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